The present invention relates to a latch and a phase synchronization circuit using the same.
Conventionally, for establishing phase synchronization of a television signal, for example, a serial digital interface (SDI) signal to an external reference signal, a jitter detector circuit is incorporated in a conventional waveform monitor. This jitter detector circuit is described in the specification of Japanese Patent Application No. 2003-41273 which is an earlier application filed by the assignee of the present application. The jitter detector circuit is used to establish phase synchronization of an SDI signal to an external reference signal, for example, an external reference frame synchronization signal in phase. More specifically, the jitter detector circuit comprises a latch for generating a frame sync signal based on the external reference frame sync signal. The latch latches the external frame sync signal derived from the external reference frame sync signal in response to a parallel clock derived from the SDI signal. A difference in phase between the external frame sync signal and parallel clock, which can be caused by an erroneous operation of the latch, i.e., an operation in an unstable region presented by the latch, is detected by the jitter detector circuit as jitter. Then, the external frame sync signal is delayed in a direction in which the phase jitter is reduced between the external frame sync signal and parallel clock. In this way, the finally established external frame sync signal is in phase sync to the parallel clock.
The jitter detector circuit described above employs a feedback control for delaying the external frame sync signal in a direction in which jitter is canceled. In addition, delay elements are used in the feedback loop. Therefore, each time jitter is detected, a feedback operation is involved for the phase synchronization. Further, the feedback control can cause a certain delay in the phase synchronization.